1. Field of the Invention
The present invention relates to a NAND flash memory. In particular, the present invention relates to a semiconductor memory device capable of storing multi-level data.
2. Description of the Related Art
A NAND flash memory is configured so that a write or read operation is collectively performed with respect to a plurality of cells arrayed in the row direction. Recently, a multi-level memory storing multi-bit data in one memory cell has been developed. For example, if four threshold (voltage) levels are set, one cell is storable with two-bit data. If eight threshold levels are set, one cell is storable with three-bit data. Further, if 16 threshold levels are set, one cell is storable with four-bit data.
Scale reduction of the cell greatly advances; as a result, there is a tendency for capacitance coupling between neighboring cells to increase. For this reason, there is a problem that the threshold level of the previously written cell changes due to a write operation of the neighboring cell. In a NAND flash memory, data is written from a memory cell on the side of a source line. For this reason, a memory cell on the side of a bit line is written, and thereby, the threshold voltage of the previously written memory cell shifts. Therefore, a write method of preventing a shift of threshold voltage due to capacitance coupling has been developed (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
The shift of the threshold voltage by capacitance coupling with neighboring cell is generated between a plurality of memory cells connected to one word line. Specifically, if multi-level data is written, write is completed from a memory cell having a low threshold voltage. For this reason, the following problem arises. Namely, a high threshold voltage is written to a memory cell adjacent to the memory cell written with a low threshold voltage. In this case, the threshold voltage of the previously written memory cell of low threshold voltage shifts to a higher threshold voltage due to capacitance coupling with a memory cell written to a high threshold voltage. For this reason, the distribution width of the low threshold voltage widens, and thus, the potential difference between high threshold voltage and low threshold voltage becomes narrow. If the potential difference between threshold voltage distributions becomes narrow, the read margin is reduced, and further, the possibility of a read error being generated becomes high. Therefore, it is desired to provide a semiconductor memory device capable of preventing a shift of threshold voltage due to capacitance coupling with neighboring cells.